NASA has selected SiFive, an American startup specializing in the development of RISC-V processors, to provide the “processor core” of the space agency’s next HPSC (High-Performance Spaceflight Computing) processor. The agency announced last June that its HPSC project aims to develop a new computing technology for spaceflight that will have computing power “at least 100 times” that of current computers developed almost 100 years ago.
These new processors should not only be radiation-resistant, but also run at minimal power and shut down when not needed, while still being able to land spacecraft on Mars and help astronauts in space. NASA Jet Propulsion Laboratory (JPL) engineers are leading the development of HPSC to create multi-core chips and their working software. The HPSC must process data 100 times faster than existing “space” computers due to power limitations.
That’s why the space agency eventually turned to SiFive, a maker of RISC-V chips, to help replace its aging spaceflight computers. According to SiFive, NASA’s HPSC will use an eight-core SiFive X280 “Intelligence” RISC-V vector core along with four other SiFive RISC-V cores.
The chip designer claims that the X280 has demonstrated 100 times the speed required by NASA HSPC and is suitable for applications requiring high bandwidth, single-wire performance and power constraints. “Our SiFive RISC-V intellectual property allows NASA to benefit from the support, flexibility and long-term viability of the growing global RISC-V ecosystem,” said Jack Kang, business development manager at SiFive.
Winning the RISC-V Standard
NASA’s choice of SiFive is a small but important victory for the RISC-V (pronounced “risk-five”) standard. The latter was invented by professors David Patterson and Krste Asanovich of the University of California at Berkeley 12 years ago. Developers are free to change the instruction set architecture (ISA) of a RISC-V chip, which defines how the chip’s hardware works. This distinguishes it from Intel’s proprietary x86 ISAs that dominate PCs and servers, and the Arm instructions licensed by Arm Ltd to most smartphone manufacturers, which have proven popular for M1 chips from, for example, Apple.
Intel is also seeing opportunities in RISC-V chips after it launched Intel Foundry Services (IFS) last year and returned to making chips for others. In February, Intel joined RISC-V as a core member and, together with IFS, announced a $1 billion fund to improve tools for x86, Arm, and RISC-V ISA. Intel is also making high-performance RISC-V cores from startup Ventana Microcro available to IFS.
In August, NASA’s Jet Propulsion Laboratory announced that it had selected Microchip Technology, a developer of industrial embedded control systems, to develop the HPSC processor. Microchip Technology was responsible for the architecture, design, and delivery of the HPSC processor for three years under a $50 million contract. NASA’s announcement does not mention RISC-V, but in June Microchip announced the industry’s first field-programmable gate array (FPGA) based on RISC-V.
According to Microchip, its design will allow NASA to take advantage of “a complete Ethernet network, advanced artificial intelligence and machine learning, and connectivity support.”